This invention relates to differential bang-bang phase detection (BBPD) methods and circuits having reduced latency. Methods and circuits are provided to improve the performance of BBPD circuits at high data rates.
The transmission of data at high data rates increasingly depends on the performance of the clock data recovery (CDR) that is used to recover the transmitted data signal from the received signal. High performance CDR circuitry is essential to accurately extract timing information from high-frequency signals and to recover the transmitted data signal from the received signal. In many digital communications applications and circuits, the performance of the CDR circuitry used in the application limits the operating frequency and data-rate of the communication circuit. Improved CDR circuitry is therefore needed in order to increase the data-rate and operating frequency of the communications applications.
The use of bang-bang phase detector circuits allows the VCO to run at one-half the frequency of the data signal. The use of BBPD circuits thereby allows communications applications to run substantially faster than the VCOs their operation depends on. However, the BBPD circuits themselves operate at the full data-rate of the received signal, and have therefore become the bottleneck of the communications applications. In order to operate at very high data-rates, BBPD circuits must output well-balanced up and down pulses to a charge pump used to regulate the VCO control voltage level. BBPD circuits must also operate with minimal jitter and with minimal latency.
It is an object of the present invention to provide improved bang-bang phase detection methods and circuits for use in high-speed, high data-rate communications applications.